(1) Field of the Invention
The present invention relates to a solid-state image sensor and a method for its fabrication, and more particularly to an interline-transfer CCD image sensor and its fabrication method.
(2) Description of the Related Art
In order to assist the understanding of the invention, a conventional interline-transfer CCD image sensor of the kind to which the present invention relates is first explained. As diagrammatically shown by a block diagram in FIG. 3, such a conventional image sensor is constituted by an image region 1, a horizontal CCD register 2, and a charge detection section (an output section) 3. A plurality of unit pixels are arranged in a matrix form in the image region 1. Each unit pixel 4 consists of a vertical CCD register 5, a photodiode 6, a read-out gate 7 for reading out a signal charge to the vertical CCD register 5 from the photodiode 6, and an element isolation region 8 outside the region of the pixel. The charge detection section 3 is provided at the left-hand end of the horizontal CCD register 2 in the image region 1.
In the unit pixel 4, as shown by a plan view in FIG. 1A and by a sectional view in FIG. 1B with the section taken along line 1B--1B in FIG. 1A, there are a P-type well 10 formed at a main surface side of an N-type silicon substrate 9 and an N-type region 13 formed in the well 10 and constituting the photodiode. In the well 10, there are also formed a P-type well 14 constituting the vertical CCD register and an N-type buried channel layer 15 on a surface of the P-type well 14. A P.sup.+ -type region 16a is formed on a surface of the element isolation region 8 and a P.sup.+ -type surface layer 17 for the reduction of noise is formed on a surface of the N-type region 13.
With the recent demand for miniaturization of CCD image sensors, a pixel size is being increasingly reduced. For example, in a 1/4 inch format 380k pixel CCD of an NTSC type, the pixel size is as small as 4.8 .mu.m(H).times.5.6 .mu.m(V) and, in a 2/3 inch format 2M pixel CCD, the pixel size is as small as 5.0 .mu.m(H).times.5.0 .mu.m(V). However, as the size of the pixel is reduced, the area of the photodiode is also reduced, thus inevitably leading to a decrease in sensitivity. In order to enhance the photoelectric conversion efficiency per unit area, it is effective to arrange that the PN junction of the photodiode be positioned at a deep location in the substrate. In order to realize this, it is known to arrange that the P-type well layer 10 and the N-type region 13 constituting the photodiode be formed at a deep location by a high energy ion-implantation process.
A conventional method for fabricating the structure described above is explained with reference to FIGS. 2A, 2B and 2C. For the fabrication of the structure shown in FIG. 2A, the well 10 having an impurity concentration of about 5.0.times.10.sup.14 cm.sup.-3 to 5.0.times.10.sup.15 cm.sup.-3 is formed, using a mask 12, on the N-type silicon substrate 9 by ion-implantation of boron at a high energy of 1-2 MeV. Next, as shown in FIG. 2B, the N-type region 13 having an impurity concentration of about 1.0.times.10.sup.16 cm.sup.-3 to 1.0.times.10.sup.17 cm.sup.-3 is formed by ion-implantation of phosphorus at a high energy of 400-500 keV followed by activation. Also, the well layer 14 and the buried channel layer 15 are formed by respective ion-implantations. Thereafter, the element isolation region is formed by ion-implanting twice as will now be explained. First, a thin resist film 19 having an opening 18 with a width of 0.6 .mu.m and having a thickness of about 1 .mu.m is formed. The P-type region 16 having an impurity concentration of about 1.0.times.10.sup.17 cm.sup.-3 to 1.0.times.10.sup.18 cm.sup.-3 is formed by ion-implantation of boron at a high energy of about 20 keV followed by activation. As shown in FIG. 2C, a thick resist film 21 with a thickness of about 2 .mu.m having an opening 20 with a width of 0.6 .mu.m is formed and, by ion-implantation of boron at an energy of 100-200 KeV and subsequent activation, a P-type region 22 having an impurity concentration of about 5.0.times.10.sup.15 cm.sup.-3 to 5.0.times.10.sup.16 cm.sup.-3 is formed in a region having a depth of 0.2 .mu.m to 1.0 .mu.m. In this way, the formation of the element isolation region 8 constituted by the P-type region 22 and the P.sup.+ -type region 16a is completed.
Now, the reason that the two separate ion-implantations are carried out for the formation of the element isolation region is explained. FIG. 4 shows a first-order impurity concentration distribution in the depth direction of the substrate at the element isolation region 8. The depth from the surface of the substrate is given in the axis of abscissas and the impurity concentration is given in the axis of ordinate. The P-type well 10 is formed by high energy ion-implantation so that the peak of the impurity concentration exists at a deep position of the substrate. On the other hand, since the P.sup.+ -type region 16a is formed by low energy ion-implantation, the peak of the impurity concentration exists near the surface of the substrate. Therefore, where the element isolation region is formed only by the P.sup.+ -type region 16a, the P-type impurity concentration becomes extremely low in the vicinity of the depth D shown in FIG. 4. For this reason, the P-type region 22 whose peak of the impurity concentration exists in the vicinity of the depth D is formed by the high energy ion-implantation as used in the formation of the P.sup.+ -type region 16a. This ensures the function of element isolation.
As explained above, in order to form the P.sup.+ -type region 16a by utilizing a 20 keV ion-implantation, a 1 .mu.m thick resist film 19 may serve as a mask. However, the P-type region 22 is formed by a 100-200 keV ion-implantation so that it is necessary to use the resist film 21 with a thickness of about 2 .mu.m for it to be used as a mask. This is the reason that the resist film formation process is required to be carried out in two steps, and this leads to a problem in increasing the fabrication steps and cost. Also, with the resist film having a thickness of about 2 .mu.m, the limit in the present-day technology is to open a space of about 0.6 .mu.m and it is difficult to narrow the space any further. Also, as shown in FIG. 5A, where the ions are implanted with a tilt angle of 7.degree. being provided in order to prevent the channeling, the bottom surface is shadowed only by about 0.1 .mu.m in the case of the 1 .mu.m thick resist film. However, as shown in FIG. 5B, in the case of the space between the 2 .mu.m thick resist films, the bottom surface is shadowed by about 0.35 .mu.m, which means that more than half of the ion-implantation width of 0.6 .mu.m is shadowed, thus making it impossible to carry out a satisfactory ion-implantation. Thus, any further ultra-fine patterning is impossible.